In the semiconductor industry, the IC manufacturers are facing enormous pressure to constantly develop improved technologies that will allow the electronic circuitry in the ICs to become ever smaller. For transistors having dimensions of less than 0.4 micron (which is typically called as the submicron region), the resolution limits of conventional photolithography technology are approached. As a result, it becomes difficult to control the yield rate.
FIGS. 1A through 1C schematically show the main steps of the conventional approach in fabricating MOS (Metal-Oxide-Semiconductor) gate having a pair of sidewall spacers on two opposing sides of the gate. FIG. 1A shows that a polysilicon layer 1 is deposited on a substrate 2 with a thin oxide layer 3 separating the polysilicon layer and the substrate. A positive resist 4 is formed on the polysilicon layer using fine line patterning. After etching, a gate electrode 5 is formed.
In order to eliminate a hot carrier effect, a lightly doped drain (LDD) structure 6, which contains two LDD sub-regions, is often formed, via impurity implantation, in the substrate using the gate electrode 5 as a mask. Then, a pair of sidewall spacers 7 are formed on the two opposing sides of the gate 5. Finally, heavily doped regions are formed via heavy impurity implantation using the gate electrode 5 and the sidewall spacers as mask, to form drain 8 and source 9, respectively.
In the conventional process as described above, the step of fine line patterning of the photoresist layer is a critical step in defining the gate and the channel dimension of the MOS. The variation of the dimension of the gate and thus the dimension of the channel of the MOS is dictated by the variation of the photolithography technique. As the dimension of MOS approaches the deep submicron region (typically less than 0.4 microns), the device performance becomes marginal (i.e., a small error can cause the device to fail), and a tighter control in the critical dimension (CD) of the gate pattern becomes essential. This has led to the development of more precise photoresist systems such as the inclusion of an anti-reflection layer, DUV lithography systems, etc. However, these techniques are still in the experimental stage, and there are concerns as to whether they possess the requisite stability. Furthermore, even these techniques should eventually become successful, they may not be cost-effective.
U.S. Pat. No. 5,270,234 discloses a method for fabricating deep submicron transistors which employs only optical lithography and involves the formation of a relative wide aperture using optical techniques. In the process disclosed in the '234 patent, an aperture is formed in a polished layer having a dimension that is considerably larger than the final channel width and within the limits of the lithography. Sidewalls are formed within the aperture in a controllable manner to determine the final channel width of the transistor. The thickness of the sidewalls is maintained during the fabrication process by the use of a two-component sidewall and a selective etch, so that the etching process that determines the final channel dimension does not change the sidewall thickness. The process disclosed in the '234 may have some technical but it is relatively complicated and may not be cost effective.
U.S. Pat. No. 5,374,575 discloses a method for fabricating LDD MOS transistors having a lightly doped drain structure capable of simplifying the fabrication and improving characteristics of the transistor. In a highly integrated system, such as the submicron system, a high electric field may occur at edge portions of the gate electrode causing the generation of hot carriers. The hot carriers serve to degrade the operation characteristic of MOS transistors and reduce the life thereof. The '375 illustrates the importance of having a well defined dimension for the gate electrode; however, it does not teach or suggest method which will allow MOS manufacturers to relax the dimensional precision requirement of lithophotography technique when fabricating submicron MOS transistors.
U.S. Pat. No. 5,538,913 discloses a process for fabricating submicron MOS transistor devices with a full-overlap lightly-doped drain. With the process disclosed in the '913 patent, the gate electrode comprises a conducting layer and a pair of conducting sidewall spacers, and a p-type diffusion region is formed by ion implantation between and below the pair of conducting sidewall spacers to prevent punch-through of the channel region. The MOS transistor fabricated from the '913 has a gate electrode of uniform width.
At the present time, it appears that there is no available method that will satisfactorily relax the dimensional precision requirement of the photolithography technique for fabricating deep submicron MOS transistors. It is highly preferred that any method that can be developed will be able to utilize currently existing technology so as to allow IC manufacturers to defer the need for expensing new capitals, while significantly improving the process yield in fabricating deep submicron MOS transistors.